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INTEGRATED CIRCUITS
DATA SHEET
PCF8832 STN RGB - 384 output column driver
Preliminary specification 2002 Aug 16
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.15.1 7.15.2 7.16 7.17 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION I/O buffer and interface Configuration control Oscillator Display data RAM Address counter Display address counter Command decoder DC-to-DC converter LCD power supply Internal reset Timing generator Row driver control Column drivers and data latches LCD waveforms and DDRAM to data mapping Frame rate control Frame rate control with 9 frames Frame rate control with 7 frames Waveforms with frame inversion or n-line inversion DDRAM addressing INSTRUCTIONS Function sets NOP Reset Software reset Power-down Vertical or horizontal addressing Display on/off Partial Mode Scroll mode Double line mode 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 10 10.1 10.2 11 11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.2 12.3 13 14 15 16 17 18 19 20 21 22 23 Set Y-address Set X-address Programming VCOL Calculation of VH Programming of VH(reg) INTERFACES Interface definitions General protocol PARALLEL INTERFACES 6800-type parallel interface 8080-type parallel interface SERIAL INTERFACES
PCF8832
Serial peripheral interface Write mode Read mode (only command register) Serial interface (3-line) Write mode Read mode (command register only) I2C-BUS INTERFACE Characteristics of the I2C-bus (Hs-mode) System configuration Bit transfer Start and stop conditions Acknowledge I2C-bus Hs-mode protocol Command decoder LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION INTERNAL PROTECTION CIRCUITS BONDING PAD INFORMATION TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
1 FEATURES
PCF8832
* LCD controller or column driver * 384 column outputs (128 x RGB) * Display data RAM 168 x 128 (RGB) * 256 colours (RGB = 332) * Blue intermediate grey scales are alterable with a command * Interface compatibilities: - I2C-bus - 8-bit parallel interface (8080 Intel CPU or 6800 Motorola CPU) - 3-line or 4-line Serial Peripheral Interface (SPI) - 3-line serial interface * Display features: - Area scrolling - Partial display mode with MUX rate 1 : 8 to 1 : 160 - Landscape or portrait mode - Software-programmable grey scale method - N-line inversion * On-chip: - Oscillator for display system requires no external components (external clock is also possible) - Generation of VCOL and VM - Switching regulator controller for generation of row voltages (VH and VL) - Row-driver control and configuration logic * Logic supply voltage range from 1.5 to 3.3 V * Analog supply voltage range from 2.4 to 3.5 V for VCOL generation 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8832U - chip with bumps in tray DESCRIPTION VERSION - * Analog supply voltage range for VH and VL generation: 2.4 to 3.5 V * Display supply voltage range from 2.5 to 4.0 V * Low power consumption, suitable for battery operated systems * CMOS compatible inputs * Manufactured in silicon gate CMOS process * Optimizes layout for COF, COG and TCP assembly. 2 APPLICATIONS
* Mobile phones * Personal Digital Assistant (PDA) * Automotive information systems * Point-of-sale terminals * Instrumentation. 3 GENERAL DESCRIPTION
The PCF8832 column driver is a low power CMOS LCD controller, column driver and power supply controller that drives colour STN displays together with a suitable row driver. The column driver offers four microcontroller interfaces (8080-type system, 6800-type system, SPI and I2C-bus).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
5 BLOCK DIAGRAM
PCF8832
handbook, full pagewidth
C0 to C383
384 FBQ VDD1 VDD3 VSS1 VM LCK VCOL VDD1 LCD POWER SUPPLY VDD1 COLUMN DRIVERS VDD1 OSCILLATOR DATA LATCHES MATRIX LATCHES VDD2 VSS2 VCOL CA1 CA2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 TIMING GENERATOR DISPLAY DATA RAM MATRIX DATA RAM ROW CONTROL OSC VDD1 INTERNAL RESET RESROW RES
VDD2
RCLK RP FI
DC/DC CONVERTER
SVM R1F SW1 SW2
VDD1
VDD1 FRC CONTROLLER
VDD1
ADDRESS COUNTER VDD1 DISPLAY ADDRESS COUNTER TP4 TP3 TP2 TP1 TP0
PCF8832
VDD1 COMMAND DECODER
VDD1 VDD1
5
ID2 ID1 ID0
I/O BUFFER INTERFACES
CONFIGURATION CONTROLLER
3
MGW658
WR/RW/SCLK
PS2, PS1, PS0
CS/SCE
D/C
RD/E
AOFF
D4/SA1
D5/SA0
SDACK
D0/SDI
D1/SDO
LPOS
Fig.1 Block diagram.
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CSCD
FSYN
D6
SCL
SDA
D2
D3
D7
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
6 PINNING SYMBOL C0 to C47 C48 to C71 C72 to C311 C312 to C335 C336 to C383 FSYN RCLK RP FI SVM RESROW R1F SW1 SW2 VM LCK T8 T7 T6 FBQ T4 VCOL CA1 CA2 VSS2 VSS1 TP0 TP1 TP2 TP3 TP4 T1 OSC T5 T2 ID0 ID1 ID2 LPOS CSCD 2002 Aug 16 PAD(1) 184 to 231 235 to 258 261 to 122 2 to 25 29 to 76 77 78 79 80 81 82 83 84 85 86 to 91 92 93 94 95 96 97 98 to 103 104 to 109 110 to 115 116 to 121 122 to 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 I I input indicating a left-sided chip configuration setting 5 I manufacturer code input; note 6 I I I test input; note 4 PS PS I system ground system ground trimming inputs for vH(reg) I O I/O PS I feedback input from inductive DC-to-DC convertor test output; note 3 HIGH-level column driving voltage capacitor connections for DC-to-DC convertor I/O I/O I/O I/O O I/O O O O I/O PS O I test input/output row driver clock input/output start frame scan input/output inversion signal input/output select row-off level output row driver reset input/output output to select shift register order output to swap/no swap register 1 output to swap/no swap register 2 TYPE O LCD column outputs DESCRIPTION
PCF8832
MID-level column driving voltage (level between VCOL and VSS) output clock for the switching regulator test inputs; note 2
external clock input or external resistor connection; note 5 test inputs; note 4
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
SYMBOL AOFF PS0 PS1 PS2 VDD1 VDD2 VDD3 T9 T10 D0/SDI D1/SDO D2 D3 D4/SA1 D5/SA0 D6 D7 RES CS/SCE RD/E WR/RW/SCLK D/C T3 SDA SDACK SCL Notes
PAD(1) 142 143 144 145 146 to 151 152 to 157 158 to 160 161, 162 163, 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179, 180 181 182, 183
TYPE I I
DESCRIPTION analog circuits on/off switching input serial or parallel interface mode setting inputs
PS PS PS I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I O I O I
logic power supply voltage capacitive booster supply voltage analog power supply voltage test input; note 7 test input; note 7 parallel or serial data input/output parallel or serial data input/output parallel data input/output parallel data input/output parallel data or I2C-bus slave address input/output parallel data or I2C-bus slave address input/output parallel data input/output parallel data input/output external reset input, active LOW chip select parallel interface or serial chip enable input read clock (8080) or clock (6800) input write clock (8080) or read write selector (6800) or serial clock input data or command indicator input test output; note 3 I2C-bus data input I2C-bus acknowledge output I2C-bus clock input
1. Dummy pads are located at positions 1, 26, 27, 28, 232, 233, 234, 259 and 260. 2. Must be connected to VM in the application. 3. Must be left open-circuit in the application. 4. Must be connected to VSS1 in the application. 5. If an external clock is applied, the internal oscillator must be switched off with a software command. 6. Pads ID2, ID1 and ID0 must be connected; manufacturer code recommended for Philips ID2 = ID1 = ID0 = 0. 7. Must be connected to VDD1 in the application.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7 7.1 FUNCTIONAL DESCRIPTION I/O buffer and interface 7.6 Display address counter
PCF8832
The interface is the connection between the outside world and PCF8832. One of five industrial standard interfaces can be selected using the interface configuration inputs PS2, PS1 and PS0. 7.2 Configuration control
The display is generated by continuously reading-out rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set via the interface. 7.7 Command decoder
It is possible to configure the PCF8832s to use external voltages, see Table 2. Table 1 Default configuration settings INPUT CSCD FSYN LPOS Table 2 Analog circuit configuration EFFECT analog part active analog part switched off, analog voltages are input through VCOL, VM DEFAULT VALUE 0 0 1
The command decoder identifies command words arriving at the interface and routes the following data bytes to their destination. 7.8 DC-to-DC converter
The voltage multiplier generates the required column voltage VCOL. Pins CA1 and CA2 must be connected to an external capacitor. If the capacitive DC-to-DC converter is switched off by AOFF = 1, then VCOL must be supplied externally. 7.9 LCD power supply
ANALOG SWITCHING0 AOFF = 0 AOFF = 1
The LCD power supply block generates the row voltage V COL level VM (equivalent to ------------ ). If the LCD power supply is 2 switched off by AOFF = 1, then VM must be supplied from an external source. 7.10 Internal reset
7.3
Oscillator
The on-chip oscillator provides the clock signal for the display system. An external clock signal, if used, is connected to the OSC input. In this case the internal oscillator must be switched off by a software command. To improve the timing accuracy there is an external resistor option. If this option is used, the external resistor must be connected between OSC and VDD1 and the appropriate register must be set. If the internal resistor is selected, the OSC input must be left open-circuit. 7.4 Display data RAM
The internal reset circuit handles hardware and software resets, provides the reset signal required internally and controls the reset signal for the row driver IC. 7.11 Timing generator
The timing generator produces the various signals required to coordinate the column driver with the row driver. 7.12 Row driver control
The Display Data RAM (DDRAM) is a 128 x 9 x 168-bit static RAM for display data storage. During RAM access, data is transferred to the DDRAM via the interface. 7.5 Address counter
The row driver IC is controlled completely by commands from the column driver. 7.13 Column drivers and data latches
The address counter sets the addresses of the display data RAM for writing operations.
The LCD drive section includes 128 x 3 column outputs (C0 to C383) which should be connected directly to the LCD. The column output signals are generated in accordance with the data in the display latches. The data are loaded from the display RAM when the corresponding row signal is active. Unused column outputs should be left open-circuit when less than 384 columns are required.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.14 LCD waveforms and DDRAM to data mapping
frame n
VH VCOL VM VSS VL VH VCOL VM VSS VL VH VCOL VM VSS VL VH
PCF8832
frame n + 1 Vstate1 (t) Vstate2 (t)
ROW 0 R0(t)
ROW 1 R1(t)
COL 0 C0(t)
COL 1 C1(t)
VCOL VM VSS VL
VH - VSS VH - VCOL
Vstate1(t)
VM - VSS VM - VCOL VM - VSS VM - VCOL VL - VSS VL - VCOL VH - VSS VH - VCOL
Vstate2 (t)
VM - VSS VM - VCOL VM - VSS VM - VCOL VL - VSS VL - VCOL
0 1 2 3 4 5 6 7 8 ...
...159 0 1 2 3 4 5 6 7 8 ...
... 159
MGW659
(1) Vstate1(t) = R0(t) - C1(t). (2) Vstate2(t) = R1(t) - C1(t).
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
red green blue RGB
DDRAM
Y address 0 top of LCD R0 R1 R2
Y address 1
Y address 2
Y address 3
R8
Y address 4
red green blue
LCD
Y address 158
Y address 159
Y address 160
R159 Y address 167
MGW660
Fig.3 DDRAM-to-display mapping.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.15 Frame rate control
PCF8832
The FRC controller generates the RGB grey scales by means of frame rate control. There are two FRC options, selectable via software commands, to give 9-frame or 7-frame working. For every pixel, eight shades of grey are created over the number of frames of the selected option.
handbook, full pagewidth
1 grey scale ratio
0 Voff(rms) Von(rms)
Vpixel(eff)
MGU592
Fig.4 Grey scale ratio as a function of effective pixel voltage.
handbook, halfpage
red
green
blue
b2 b1
r2
g2
bl2
r1 r0
g1 g0
bl1 bl0
b0
column bits
RGB pixel in DDRAM
MGU593
Fig.5 Pixel bit definition.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.15.1 Table 3 b2 0 0 0 0 1 1 1 1 FRAME RATE CONTROL WITH 9 FRAMES Grey scale encoding; 9 frames b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 EFFECTIVE PIXEL VOLTAGE
0 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9
PCF8832
Voff(rms)
Von(rms)
Frame handbook, full pagewidth
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
Super-frame Row R0 Row R1 Row R2
Row R158 Row R159
Column
b0
b1
b2
b1
b2
b0
b2
b1
b2
MGW663
Fig.6 FRC driving scheme with 9 frames.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.15.2 Table 4 b2 0 0 0 0 1 1 1 1 FRAME RATE CONTROL WITH 7 FRAMES Grey scale encoding; 7 frames b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 EFFECTIVE PIXEL VOLTAGE
0 1 2 3 4 5 6 7 7 7 7 7 7 7 7 7
PCF8832
Voff(rms)
Von(rms)
handbook, full pagewidth
Frame
n
n+1
n+2
n+3
n+4
n+5
n+6
Super-frame Row R0 Row R1 Row R2
Row R158 Row R159
Column
b2
b1
b2
b0
b2
b1
b2
MGW664
Fig.7 FRC driving scheme with 7 frames.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.16 Waveforms with frame inversion or n-line inversion
PCF8832
The PCF8832 offers the possibility of using different waveforms. Figure 8 shows the standard Alt and Pleshko (APT) frame inversion waveforms. N-line inversion, synchronized and asynchronous to the frame, are shown in Figs 9 and 10. Selection of one of these options is made via software command.
handbook, full pagewidth
frame n
frame n + 1
FI
R0
R1
R2
R3
R4
R5
R6
R7
R158
R159
MGW665
Fig.8 Frame inversion.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
frame n
frame n + 1
FI
R0
R1
R2
R3
R4
R5
R6
R7
R158
R159
MGW666
Fig.9 N-line inversion, synchronized with frame.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
frame n
frame n + 1
FI
R0
R1
R2
R3
R4
R5
R6
R7
R158
R159
MGW667
Fig.10 N-line inversion, not synchronized with frame.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
7.17 DDRAM addressing
PCF8832
In vertical addressing mode (V = 1), the Y-address increments after each byte. After the last Y-address (Y = ye), Y wraps around to ys and X increments to address the next column. In horizontal addressing mode (V = 0), the X-address increments after each byte. After the last X-address (X = xe), X wraps around to xs and Y increments to address the next row. After the very last address (X = xe and Y = ye) the address pointers wrap around to address (X = xs and Y = ys). For flexibility in handling a wide variety of display architectures, the commands `RAM data addressing' and `data control' define flags MX, MY and L, which allows mirroring of the X and Y-addresses and selection of landscape or portrait mode. All combinations of flags are allowed. The available combinations of writing to the display RAM are shown in Figs 12 to 17. When MX, MY, V or L are changed, the data must be rewritten to the display RAM.
Data is written byte-wise into the RAM matrix of the PCF8832 as illustrated in Fig.11. The display RAM has a matrix of 168 x 128 x 9 bits. RAM locations are addressed by the address pointers. The address ranges are X = 0 to X = 127 (7F) and Y = 0 to Y = 167 (A7H). Addresses outside of these ranges are not allowed. Before writing to the RAM, a window must be defined into which it can be written. The window is programmable via the command registers with xs and ys designating the start address, and xe and ye designating the end address. If, for example, the whole display content is to be written, the window is defined by the following values: xs = 0 (0H), ys = 0 (0H), xe = 127 (7FH) and ys = 159 (9FH).
D7 D6 D5 D4 D3 D2 D1 D0 handbook, full pagewidth R2 R1 R0 G2 G1 G0 B1 B0 R2 R1 R0 G2 G1 G0 Bi2 Bi1 Bi0 display byte sent via interface pixel information stored in display RAM
xs
D7 D4 Diii D6 D3 Dii
xe 0 1
ys
D5 D2 Di R GB
2 3 4
ye
5 6 7
Y address
167 0 X address 127
MGW668
Fig.11 RAM format and addressing.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
xs
handbook, halfpage 0
xe
MGW669
xs
handbook, halfpage 0
xe
MGW670
ys
ys
Y address
ye
Y address
ye
167 0 X address 127
167 0 X address 127
a. V = 0, MX = 0, MY = 0 and L = 0.
b. V = 1, MX = 0, MY = 0 and L = 0.
Fig.12 Sequence of writing data bytes into RAM as a function of vertical control bit V.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
xs
handbook, halfpage 0
xe
MGW671
xe
handbook, halfpage 0
xs
MGW672
ys
ys
Y address
ye
Y address
ye
167 0 X address 127
167 127 X address 0
a. V = 0, MX = 0, MY = 0 and L = 0.
b. V = 0, MX = 1, MY = 0 and L = 0.
xs
handbook, halfpage 167
xe
MGW673
xs
handbook, halfpage 167
xe
MGW674
ye
ye
Y address
ys
Y address
ys
0 0 X address 127
0 127 X address 0
c. V = 0, MX = 0, MY = 1 and L = 0.
d. V = 0, MX = 1, MY = 1 and L = 0.
Fig.13 Sequence of writing data bytes into RAM with horizontal addressing (V = 0) as a function of mirror control bits MX and MY.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
xs
handbook, halfpage 0
xe
MGW675
xe
handbook, halfpage 0
xs
MGW676
ys
ys
Y address
ye
Y address
ye
167 0 X address 127
167 127 X address 0
a. V = 1, MX = 0, MY = 0 and L = 0.
b. V = 1, MX = 1, MY = 0 and L = 0.
xs
handbook, halfpage 167
xe
MGW677
xs
handbook, halfpage 167
xe
MGW678
ye
ye
Y address
ys
Y address
ys
0 0 X address 127
0 127 X address 0
c. V = 1, MX = 0, MY = 1 and L = 0.
d. V = 1, MX = 1, MY = 1 and L = 0.
Fig.14 Sequence of writing data bytes into RAM with vertical addressing (V = 1) as a function of mirror control bits MX and MY.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
X
0 Y 0
Y address
Y address
127 167 167 0 X address 127 X address 0
MGW679
a. Portrait (L = 0).
b. Landscape (L = 1).
Fig.15 Principle of landscape/portrait switching using landscape control bit L.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
X xs 0 handbook, halfpage Y xe
MGW680
X xe 0 handbook, halfpage ys ys Y xs
MGW681
Y address
ye
Y address
ye
127 0 X address 167
127 167 X address 0
a. V = 0, MX = 0, MY = 0 and L = 1.
b. V = 0, MX = 1, MY = 0 and L = 1.
xs 127 handbook, halfpage
xe
MGW682
xe 127 handbook, halfpage ye
xs
MGW683
ye
Y address
ys
Y address
ys
Y 0 0 X X address 167 0 167 X address X 0
Y
c. V = 0, MX = 0, MY = 1 and L = 1.
d. V = 0, MX = 1, MY = 1 and L = 1.
Fig.16 Sequence of writing data bytes into RAM with horizontal addressing and in landscape mode as a function of mirror control bits MX and MY.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
X xs 0 handbook, halfpage Y xe
MGW684
X xe 0 handbook, halfpage ys ys Y xs
MGW685
Y address
ye
Y address
ye
127 0 X address 167
127 167 X address 0
a. V = 1, MX = 0, MY = 0 and L = 1.
b. V = 1, MX = 1, MY = 0 and L = 1.
xs 127 handbook, halfpage
xe
MGW686
xe 127 handbook, halfpage ye
xs
MGW687
ye
Y address
ys
Y address
ys
Y 0 0 X X address 167 0 167 X address X 0
Y
c. V = 1, MX = 0, MY = 1 and L = 1.
d. V = 1, MX = 1, MY = 1 and L = 1.
Fig.17 Sequence of writing data bytes into RAM with vertical addressing and in landscape mode as a function of mirror control bits MX and MY.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
8 INSTRUCTIONS There are three types of instructions: * Defining display configuration * Miscellaneous instructions * Setting X and Y-addresses.
PCF8832
The PCF8832 communicates with the host via two 8-bit parallel interfaces, a 3-line or a 4-line serial peripheral interface or an I2C-bus interface. Processing of the instructions does not require the display clock. The PCF8832 has two access types, those defining the operating mode of the device (instructions) and those filling the display RAM. The latter are the most frequently used. Efficient data transfer is achieved by auto-incrementing RAM address pointers.
The initial sequence to be sent to the IC is given in Table 5. Table 5 Initial instruction sequence REGISTER VALUE (HEX) 06 00
CONTROL BYTE (HEX) 85 A2
Table 6 Command register Only command register addresses shown are allowed; after reset the registers go to their default value; is equivalent to don't care; see Table 7 for explanation of control bits used ADR (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 D7 0 0 0 0 0 0 xs[7] xe[7] ys[7] ye[7] NLI7 0 0 0 D6 0 0 0 0 0 xs[6] xe[6] ys[6] ye[6] NLI6 0 0 0 D5 0 0 0 0 0 xs[5] xe[5] ys[5] ye[5] NLI5 b002 b102 0 D4 0 0 0 0 0 0 xs[4] xe[4] ys[4] ye[4] NLI4 b001 b101 0 0 SPS 0 xs[3] xe[3] ys[3] ye[3] NLI3 b000 b100 D3 0 0 D2 0 MY PM 0 xs[2] xe[2] ys[2] ye[2] VMOE NLI2 b012 b112 0 D1 0 RSTA MX L DIM ER xs[1] xe[1] ys[1] ye[1] VCOE NLI1 b011 b111 0 D0 0 PD 0 V DON EC xs[0] xe[0] ys[0] ye[0] OFQ NLI0 b010 b110 CF0 DEFAULT (HEX) 00 01 00 00 00 02 00 7F 00 A7 07 00 01 27 00 00 4F 50 9F 00 00 00 05 DESCRIPTION NOP (no operation) Power-down RAM data addressing data control display settings oscillator-related bits X-ADR start; 0 xs FF X-ADR end; xs xe FF Y-ADR start; 0 ys A8 Y-ADR end; ys ye A8 IO configuration; oscillator frequency n-line inversion mapping blue scale b00; b01 mapping blue scale b10; b11 colour filter (RGB array) active area 1 start ADR active area 1 end ADR active area 2 start ADR active area 2 end ADR scroll area start ADR; DSA1 DSA2 scroll area end ADR scroll entry point set frame frequency
AA1S7 AA1S6 AA1S5 AA1S4 AA1S3 AA1S2 AA1S1 AA1S0 AA1E7 AA1E6 AA1E5 AA1E4 AA1E3 AA1E2 AA1E1 AA1E0 AA2S7 AA2S6 AA2S5 AA2S4 AA2S3 AA2S2 AA2S1 AA2S0 AA2E7 AA2E6 AA2E5 AA2E4 AA2E3 AA2E2 AA2E1 AA2E0 DSA17 DSA16 DSA15 DSA14 DSA13 DSA12 DSA11 DSA10 DSA27 DSA26 DSA25 DSA24 DSA23 DSA22 DSA21 DSA20 SEP7 0 SEP6 0 SEP5 SEP4 FFQ4 SEP3 FFQ3 SEP2 FFQ2 23 SEP1 FFQ1 SEP0 FFQ0
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
ADR (HEX) 17 18 19 1A 1B 1C 1D 1E 1F 3F Table 7
D7 0 VPR7 0 0 0 VL7 0 0 0 0
D6 0 VPR6 0 0 0 VL6 0 0 TD6 0
D5 0 VPR5 0 SLB2 SLD2 VL5 0 0 TD5 1
D4 0 VPR4 0 SLB1 SLD1 VL4 DBL 0 TD4 1
D3 FI VPR3 VPC3 SLB0 SLD0 VL3 SEC 0 TD3 1
D2 IR VPR2 VPC2 SLA2 SLC2 VL2 R1F ID2 TD2 1
D1 0 VPR1 VPC1 SLA1 SLC1 VL1 SW2 ID1 TD1 1
D0 FRCM VPR0 VPC0 SLA0 SLC0 VL0 SW1 ID0 TD0 1
DEFAULT (HEX) 0D A2 05 07 10 D1 04 00 20 -
DESCRIPTION frame inversion; FRC program VHREG program VCOL temperature compensation slopes temperature compensation slopes VOPVH limit value row driver control chip identity temperature read data software reset
Explanation of control bits used in Table 6 0 active mode no register read no mirror X no mirror Y portrait mode RAM write in X direction display off normal display no partial display mode scroll inactive internal oscillator external resistor used fLCK = 300 kHz VM is input VCOL is input asynchronous n-line inversion no frame inversion frame rate control, 7-frame method Power-down mode read value from select address mirror X mirror Y landscape mode vertical RAM write, in Y direction display on display inverse video mode partial display mode active start programmed scroll active external clock applied internal resistor used oscillator frequency at LCK output fLCK = 600 kHz VM is enabled as output VCOL is enabled as output n-line inversion related to frame frame inversion active frame rate control, 9-frame method 1
BIT PD RSTA MX MY L V DON DIM PM SPS EC ER OFQ VMOE VCOE IR FI FRCM
Row driver control DBL SEC R1F SW1 SW2 single line mode first half of RAM is displayed (DBL = 1) shift register 2 first in chain normal row shift direction REG1[0 to 79] normal row shift direction REG2[80 to 159] double line mode second half of RAM is displayed (DBL = 1) shift register 1 first in chain swapped shift direction REG1[79 to 0] swapped shift direction REG2[159 to 80]
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Preliminary specification
STN RGB - 384 output column driver
Table 8 N-line inversion (NLI[7:0] < 160) DESCRIPTION Table 11 Set frame frequency FFQ[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 Decoding of the blue bits is shown in Table 9. The data byte for one pixel contains 8 bits (RRRGGGBB). The red and green bits will be written directly to the RAM. For the blue bits, the data to be written for B[1:0] values are defined in the command register (address 0CH and 0DH). The procedure for writing the blue bits is: 1. Program the blue scale register (ADR: 0CH and 0DH) e.g. set register 0CH to 01H. 2. Send pixel information via interface; the pixel value via interface is ADH, (RRR = 101), (GGG = 011) and (B[1:0] = 01). 3. Write procedure of pixel information to display RAM: a) RRR and GGG is written directly to the RAM b) The two blue bits decide which register bits are to be used, in this example b012, b011 and b010 will be written as blue pixel information to the display RAM. Table 9 Translation of blue bits b[1:0] 00 01 10 11 REGISTER BITS 0CH and 0DH b002 b001 b000 b012 b011 b010 b102 b101 b100 b112 b111 b110 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Table 10 Column output voltage (VCOL = 100 mV) VPC[3:0] 0000 to 1111 VCOL (V) 2.5 to 4.0
PCF8832
NLI[7:0]
FRAME FREQUENCY (Hz) 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 - - - - - - - - - - - -
00000000 no n-line inversion (frame inversion) 00000001 inversion after each row 00000010 inversion after 2 rows to to to to 01100100 inversion after 100 rows 10011111 inversion after 159 rows
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
Table 12 Colour filter CF0 0 1 8.1 8.1.1 C0 R B Function sets NOP C1 G G C2 B R C3 R B C4 G G 8.1.4 C5 B R C6 R B C7 G G
PCF8832
to
C383 B R
POWER-DOWN
The `no operation' functionality is provided by the NOP register. According to the interface protocol, first the address 00H and then the register value 00H must be sent. 8.1.2 RESET
During Power-down (PD), all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system) and all LCD column outputs are connected internally to VSS. The I/O buffer and interface remain operational. When PD = 1, the PCF8832 is in the Power-down mode: * All column outputs are set to VSS (display off) * Interface is operational; commands can be executed * RAM contents are not cleared; RAM data can be written * Register settings remain unchanged. 8.1.5 VERTICAL OR HORIZONTAL ADDRESSING
The chip has a hardware and a software reset. After power-up, a hardware reset input (RES) must be applied. The hardware and software resets give the same results. After a reset the chip has the following state: * All column outputs set to VSS (display off) * RAM data undefined * Power-down mode * Command register set to default states (see Table 6). 8.1.3 SOFTWARE RESET
When V = 0, horizontal addressing is selected and the data is written into the DDRAM as shown in Fig.13. When V = 1, vertical addressing is selected and the data is written into the DDRAM as shown in Fig.14.
The software reset is applied following interface protocol: 1. Send a control byte with the software register address (3FH). 2. Send the register value (3FH). 8.1.6 DISPLAY ON/OFF
Table 13 Display mode bits DIM and DON DIM 0 0 1 1 DON 0 1 0 1 MODE all pixels off normal mode all pixels on inverse video mode Vpixel Voff(rms) pixel value: (000) = Voff(rms); (111) = Von(rms) Von(rms) pixel value: (111) = Voff(rms); (000) = Von(rms)
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
8.1.7 PARTIAL MODE
PCF8832
When setting the addresses the following condition must be ensured: 0 AA1S < AA1E < AA2S < AA2E 9FH In partial mode, the MUX rate of the driver is set automatically to the minimum required thus reducing power consumption. The appropriate operating voltages VH and VCOL must be programmed. Scroll mode cannot be used in partial mode.
The following steps must be performed to enter partial mode (PM), refer to Fig.18: 1. Set start address of active area 1 AA1S[7:0]. 2. Set end address of active area 1 AA1E[7:0]. 3. Set start address of active area 2 AA2S[7:0]. 4. Set end address of active area 2 AA2E[7:0]. 5. Enter partial mode PM = 1.
handbook, full pagewidth
display RAM
ROW 0 ROW 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ROW 144 ROW 145 152 153 154 155 ROW 146 ROW 147 ROW 148 ROW 149 ROW 150 ROW 151 ROW 152 ROW 153 ROW 154 ROW 155 ROW 156 ROW 157 ROW 158 ROW 159 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31
AA1S [7:0]
partial area 1
AA1E [7:0]
AA2S [7:0]
AA2E [7:0]
156 157 158 159 160 161 162 163 164 165 166 167
partial area 2
MGW688
Fig.18 Partial mode.
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Preliminary specification
STN RGB - 384 output column driver
8.1.8 SCROLL MODE
PCF8832
4. After the desired time interval, increment the scroll address to SEP + n for an n-line step. 5. Keep incrementing the scroll address at regular intervals. 6. Stop scroll mode SPS = 0. If DSA1 = n with 0 < n < 159 and DSA2 = 159, then only one fixed area at the top of the display is used. In this configuration the hidden part of the RAM Y-addresses 160 to 167 can be used in scroll mode.
The following steps must be performed to enter scroll mode, refer to Fig.19: 1. Define the scroll area: a) Set start address DSA1[7:0] b) Set end address DSA2[7:0]. 2. Set Scroll Entry Point SEP[7:0]. 3. Enter scroll mode by setting Start Programmed Scroll SPS = 1.
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display RAM
ROW 0 ROW 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ROW 144 ROW 145 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 ROW 146 ROW 147 ROW 148 ROW 149 ROW 150 ROW 151 ROW 152 ROW 153 ROW 154 ROW 155 ROW 156 ROW 157 ROW 158 ROW 159 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17
f area fix
DSA1 [7:0]
SEP [7:0]
ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31
s scroll area
DSA2 [7:0]
fix area
MGW689
Fig.19 Scroll mode.
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Preliminary specification
STN RGB - 384 output column driver
8.1.9 DOUBLE LINE MODE
PCF8832
Double line mode can be used in combination with the scroll mode. If SEC = 0, the first part of the RAM Y-address 0 to 79 will appear on the display in double line mode. During scroll mode, the hidden part of the RAM Y-address 80 to 167 can be scrolled-up. If SEC = 1, the second part of the RAM will be displayed.
If DBL = 1, then two rows will be selected at the same time. In this case, only the half of the RAM content can be displayed. The SEC bit selects the part of the RAM to be displayed (see Fig.20).
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display RAM
ROW 0 ROW 1 0 1 2 3 4 5 6 7 8 9 10 11 12 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19
SEC = 0
13 14 15 16 17 18 19
ROW 75 ROW 76 75 76 77 78 79 80 81 82 83 ROW 144 ROW 145 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 ROW 146 ROW 147 ROW 148 ROW 149 ROW 150 ROW 151 ROW 152 ROW 153 ROW 154 ROW 155 ROW 156 ROW 157 ROW 158 ROW 159 ROW 77 ROW 78 ROW 79 ROW 80 ROW 81 ROW 82 ROW 83
MGW690
Fig.20 Double line mode.
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Preliminary specification
STN RGB - 384 output column driver
8.2 Set Y-address 8.6 Programming of VH(reg)
PCF8832
Bits ys[7:0] and ye[7:0] define the Y-address range of the display RAM for writing data. Values of ys and ye are between 0 and 167 (A7H); ys must be smaller then ye. Table 14 Y-address range y7 0 0 0 1 1 8.3 y6 0 0 0 0 0 y5 0 0 0 1 1 y4 0 0 0 0 0 y3 0 0 0 to 0 0 1 1 1 1 0 1 166 167 y2 0 0 0 y1 0 0 1 y0 0 1 0 BANK 0 1 2
The voltage VH(reg) regulates the external row voltage level VH with the control of the external inductive DC-to-DC converter. If the external voltage VFBQ < VH(reg), the switching clock LCK will start to boost the row voltage level. If VFBQ VH(reg), the clock LCK stops to maintain the row voltage level. The following equation shows the calculation of VH(reg) VH(reg) = VH(reg)(min) + VH(reg) x fmin(VPR + TP) x VL Where VT is the signed value dependent on temperature sensor output and programmed slope VPR is an 8-bit value, set via the command register VH(reg) = 7 mV (step size of VH(reg)) VH(reg)(min) = 200 mV VL is an 8-bit value, set via the command register TP is a 5-bit signed value provided via the VH(reg) trimming inputs TP4, TP3, TP2, TP1 and TP0 fmin is a minimum function, with VL it is possible to limit the generated voltage (the low voltage limit is zero). If VL < (VPR + TP), VH(reg) will be limited to the following level V H(reg) = V H(reg)(min) + V H(reg) x VL Table 15 VH(reg) trimming VH(reg) TRIMMING INPUTS TP4 1 1 1 0 0 0 0 TP3 0 0 1 0 0 1 1 TP2 0 0 to 1 0 0 to 1 1 1 1 0 1 +14 +15 1 0 0 1 0 1 -1 0 +1 TP1 0 0 TP0 0 1 -16 -15 VALUE
Set X-address
Bits xs and xe define the X-address range of the display RAM for writing data. Values of xs, xe are between 0 and 127 (7FH); xs must be smaller then xe. 8.4 Programming VCOL
VCOL can be programmed in the range VCOL(min) = 2.5 V to VCOL(max) = 4.0 V. The following equation shows the calculation of VCOL V COL = V COL(min) + VPC x V COL Where VPC is a 4-bit value that can be set via the command register (see Table 10) VCOL = 100 mV. Regardless of the equation, the value of VCOL is limited to the range 2.5 to 4.0 V. 8.5 Calculation of VH
The following equation shows how to calculate VH. R1 and R2 are external resistors (see Fig.62). V H = V H(reg) x K RES where K RES R1 + R2 = -------------------R2
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
9 9.1 INTERFACES Interface definitions
PCF8832
Table 16 Selection of interface type PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 INTERFACE 3-line SPI 4-line SPI I2C-bus serial (3-line) 8080 MPU basic 8080 MPU 6800 MPU basic 6800 MPU READ-BACK SELECT via command bit RSTAT via command bit RSTAT via R/W in slave address via command bit RSTAT WR write strobe WR write strobe R/W = 1 R/W = 1 CS used as clock; basic protocol only basic protocol only REMARKS
Table 17 Control byte definition INTERFACE I2C-bus Parallel (8080) Parallel (6800) SPI (3-line) SPI (4-line) Serial (3-line) D7 CO CO CO CO CO CO D6 D/C 0 0 D/C 0 0 D5 ADR5 ADR5 ADR5 ADR5 ADR5 ADR5 D4 ADR4 ADR4 ADR4 ADR4 ADR4 ADR4 D3 ADR3 ADR3 ADR3 ADR3 ADR3 ADR3 D2 ADR2 ADR2 ADR2 ADR2 ADR2 ADR2 D1 ADR1 ADR1 ADR1 ADR1 ADR1 ADR1 D0 ADR0 ADR0 external signal A0 used ADR0 external signal A0 used ADR0 ADR0 external signal A0 used ADR0 first bit for DC COMMENT
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control byte D7 D6 ADR [5:0] register address (hex) ADR [5:0] 0 1 2 3 register value RV [7:0]
3F
MGW694
Fig.21 Command register addressing.
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Preliminary specification
STN RGB - 384 output column driver
Table 18 Bits CO and D/C RSTA(1) CO 0 0 0 1 1 0 1(2) 0 1 1 Notes D/C 0 1 0 1 0 1 0 1 DESCRIPTION write stream of commands, starting at register ADR[5:0] write stream of data to RAM, ADR[5:0] don't care write single command to register ADR[5:0] write single RAM data, ADR[5:0] don't care read all registers, starting at register ADR[5:0] not used read single register at ADR[5:0] not used
PCF8832
1. RSTA specifies the read or write mode of register RSTA: 0 = write mode; 1 = read mode. RSTA is used only with the serial and I2C-bus interfaces. 2. Read mode protocol for serial interfaces. 9.2 General protocol
The generally-supported protocols for programming the LCD driver are shown in Figs 22 and 23.
handbook, full pagewidth
CB
RV
CB
RV
CB
RV
MGW695
CB = control byte. RV = register value.
Fig.22 Basic protocol (D/C = 0).
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S
CBn
RVn
RV(n + 1)
RV(n + 2)
RV(n + m)
P
MGW696
S = start data transmission. CBn = control byte that points to address n. RVn = register value for register of address n. RV(n + 1) = register value for register of address n + 1. P = stop data transmission.
Fig.23 Advanced protocol (D/C = 0).
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Preliminary specification
STN RGB - 384 output column driver
10 PARALLEL INTERFACES The parallel interfaces that can be selected are the 6800-type and 8080-type 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. The selection of an interface is done with inputs PS2, PS1 and PS0, see Table 16. 10.1 6800-type parallel interface
PCF8832
shown in these figures is a register value or a control byte, depending on the mode and protocol used. Table 19 6800-type parallel interface function D/C 0 0 1 1 R/WR 0 1 0 1 OPERATION command data write read status register display data write none
The interface functions of the 6800-type parallel interface are shown in Table 19. Figures 24 to 29 show the data transfer in different modes. The transmission byte (TB)
handbook, full pagewidth
S
CB
RVn
RV(n + 1)
RV(n + 2)
RV(n + 3)
RV(n + m)
P
CS D/C RW E D [7:0] TB TB TB TB TB TB
MGW697
Fig.24 Parallel bus protocol, advanced write to register (PS[2:0] = 111).
handbook, full pagewidth
S
CB
RVn
RV(n + 1)
RV(n + 2)
RV(n + 3)
RV(n + m)
P
CS
D/C RW E D [7:0] TB
D [7:0]
TB
TB
TB
TB
TB
MGW698
Fig.25 Parallel bus protocol, advanced read from register (PS[2:0] = 111).
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Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
DRAM data
DRAM data
DRAM data
DRAM data
DRAM data
DRAM data
CS D/C RW E D [7:0] byte 1 byte 2 byte 3 byte 4 byte 5 byte 6
MGW699
Fig.26 Parallel bus protocol, write to RAM.
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S
CB
RV
CB
RV
CB
RV
P
CS
D/C
RW E D [7:0] TB TB TB TB TB TB
MGW700
Fig.27 Parallel bus protocol, basic write to register (PS[2:0] = 111).
handbook, full pagewidth
CB
RV
CB
RV
CB
RV
CS D/C
RW
D [7:0]
TB
TB
TB
TB
TB
TB
MGW701
Fig.28 Parallel bus protocol, basic write to register (PS[2:0] = 101).
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Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
CB
RV
CB
RV
CB
RV
CS D/C RW
D [7:0]
TB
TB
TB
D [7:0]
TB
TB
TB
MGW702
Fig.29 Parallel bus protocol, basic read from register (PS[2:0] = 101).
10.2
8080-type parallel interface
Table 20 8080-type parallel interface function A0 (D/C) 0 1 0 1 1 Note 1. indicates a rising edge. RD(1) 1 1 WR(1) 1 1 OPERATION command data write display data write read status register none not allowed
The interface functions of the 8080-type parallel interface are given in Table 20. Figures 30 to 34 show the data transfer in different modes. The transmission byte (TB) shown in these figures is a register value or a control byte, depending on mode and protocol used.
handbook, full pagewidth
S
CB
RVn
RV(n + 1)
RV(n + 2)
RV(n + 3)
RV(n + m)
P
CS D/C WR D [7:0] TB TB TB TB TB TB
MGW703
Fig.30 Parallel bus protocol, advanced write to register (PS[2:0] = 110).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
S
CB
RVn
RV(n + 1)
RV(n + 2)
RV(n + 3)
RV(n + m)
P
CS
D/C WR RD D [7:0] TB
D [7:0]
TB
TB
TB
TB
TB
MGW704
Fig.31 Parallel bus protocol, advanced read from register (PS[2:0] = 110).
handbook, full pagewidth
CB
RV
CB
RV
CB
RV
CS D/C WR D [7:0] TB TB TB TB TB TB
MGW705
Fig.32 Parallel bus protocol, basic write to register (PS[2:0] = 100).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
CB
RV
CB
RV
CB
RV
CS D/C WR RD D [7:0] TB TB TB
D [7:0]
TB
TB
TB
MGW706
Fig.33 Parallel bus protocol, basic read from register (PS[2:0] = 100).
handbook, full pagewidth
RAM data
RAM data
RAM data
RAM data
RAM data
RAM data
CS D/C WR D [7:0] TB TB TB TB TB TB
MGW707
Fig.34 Parallel bus protocol, write to display RAM (PS[2:0] = 100).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
11 SERIAL INTERFACES Communication with the microcontroller can also occur via a clock-synchronized serial peripheral interface. It is possible to select two different 3-line interfaces (SPI and serial interface) or a 4-line SPI. 11.1 Serial peripheral interface 11.1.1 WRITE MODE
PCF8832
The display data/command indication may be controlled either via software (3-line SPI) or the D/C select pin (4-line SPI). When the D/C pin is used, display data is transmitted when D/C is HIGH and command data is transmitted when D/C is LOW (see Figs 35 and 36). When D/C is not used, then the D/C is set via the control byte. When the 3-line SPI interface is used, the display data/command is controlled by software (see Figs 37 and 38). If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data are valid.
The SPI is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. The three lines are: SCE (chip enable), SCLK (serial clock) and SDI (serial data). For the 4-line serial interface a separate D/C line is included. The PCF8832 is connected to the serial data I/O of the microcontroller by two pins: SDI (data input) and SDO (data output) which must be connected together.
handbook, full pagewidth
S
control byte
register value
P
SCE
D/C
SCLK
SDI
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
MGW708
Fig.35 Serial bus protocol, write to register.
handbook, full pagewidth
S
control byte
display data
P
SCE
D/C
SCLK
SDI
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
MGW709
Fig.36 Serial bus protocol, write to RAM.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
S
control byte
register value
P
SCE
SCLK
SDI
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
MGW710
Fig.37 Serial bus protocol, write to register (D/C = 0 set into control byte).
handbook, full pagewidth
S
control byte
display data
P
SCE
SCLK
SDI
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
MGW711
Fig.38 Serial bus protocol, write to RAM (DC = 1 set into control byte).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
11.1.2 READ MODE (ONLY COMMAND REGISTER)
PCF8832
The PCF8832 samples the SDI data at rising edges, but shifts SDO data at falling SCLK edges. Thus the microcontroller should read SDO data at rising SCLK edges. After the read command sequence has been sent, the SDI line must be set to 3-state not later than the falling SCLK edge of the last bit (see Fig.39).
The read mode of the interface means that the microcontroller reads data from the PCF8832. To do so, the microcontroller first sends a command sequence, the PCF8832 then responds by transmitting data on the SDO line. After that, SCE is required to go HIGH (see Fig.39) and this resets the RSTA bit to write operation.
handbook, full pagewidth
S
CB (ADR [5:0] = 01H)
RV (set RSTA = 1)
CB (set read ADR = n)
RV (from ADRn)
P
SCE D/C
SCLK
SDI
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
SDO
b7 b6 b5 b4 b3 b2 b1 b0
MGW712
Fig.39 Serial bus protocol, read from register.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
11.2 Serial interface (3-line)
PCF8832
consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission. Serial bus protocol (see Fig.41): * When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE, the serial interface is initialized. * At the falling edge of SCE, SCLK must be LOW * SDI is sampled on the rising edge of SCLK * D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1); D/C is sampled with the first rising edge of SCLK * If SCE stays LOW after the last bit of a command/data byte, the serial interface expects the D/C bit of the next byte at the next rising edge of SCLK * A reset pulse with RES interrupts the transmission (the data being written into the RAM may be corrupted); the registers are cleared, then if SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte.
The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The three lines are: SCE (chip enable), SCLK (serial clock) and SDI/SDO (serial data). 11.2.1 WRITE MODE
The interface write mode means that the microcontroller writes commands and data to the PCF8832. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the byte that follows is interpreted as a control byte. The basic and the advanced protocols are supported. The command set is given in Table 6. If D/C is HIGH, the byte that follows is stored in the display data RAM. After every data byte the address counter is incremented automatically. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is
handbook, full pagewidth
transmission byte (1)
D/C
D7 MSB
D6
D5
D4
D3
D2
D1
D0 LSB
D/C
transmission byte
D/C
transmission byte
D/C
transmission byte
MGW713
(1) Transmission byte may be a command byte or a data byte.
Fig.40 Serial data stream, write mode.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
S
control byte
register value
P
SCE
SCLK
SDI
D/C
b7
b6
b5
b4
b3
b2
b1
b0
D/C
b7
b6
b5
b4
b3
b2
b1
b0
MGW714
Fig.41 Serial bus protocol, write to register with control bit in transmission.
handbook, full pagewidth
1
start data transmission
SCE = 0
2
command mode
D/C = 0
(1 SCLK cycle)
3
control byte
0
0
ADR [5:0] = n
(8 SCLK cycles)
4
command mode
D/C = 0
(1 SCLK cycle)
5
register value for ADR = n
(8 SCLK cycles)
6
command mode
D/C = 0
(1 SCLK cycle)
7
register value for ADR = n + 1
(8 SCLK cycles)
k-1
command mode
D/C = 0
(1 SCLK cycle)
k
register value for ADR = n + m
(8 SCLK cycles)
k+1
stop data transmission
SCE = 1
MGW715
Fig.42 Write sequence to register, advanced protocol.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
1
start data transmission
SCE = 0
2
command mode
D/C = 0
(1 SCLK cycle)
3
control byte
1
0
ADR [5:0] = n
(8 SCLK cycles)
4
command mode
D/C = 0
(1 SCLK cycle)
5
register value for ADR = n
(8 SCLK cycles)
6
command mode
D/C = 0
(1 SCLK cycle)
7
control byte
1
0
ADR [5:0] = l
(8 SCLK cycles)
8
command mode
D/C = 0
(1 SCLK cycle)
9
register value for ADR = l
(8 SCLK cycles)
k-3 k-2 k-1
command mode
D/C = 0
(1 SCLK cycle)
control byte
1
0
ADR [5:0] = m
(8 SCLK cycles)
command mode
D/C = 0
(1 SCLK cycle)
k
register value for ADR = m
(8 SCLK cycles)
k+1
stop data transmission
SCE = 1
MGW716
Fig.43 Write sequence to register, basic protocol.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
1
start data transmission
SCE = 0
2
command mode
D/C = 0
(1 SCLK cycle)
3
control byte
0
0
XXXXXX
(8 SCLK cycles)
4
data mode
D/C = 1
(1 SCLK cycle)
5
display data byte 1
(8 SCLK cycles)
6
data mode
D/C = 1
(1 SCLK cycle)
7
display data byte 2
(8 SCLK cycles)
k-1
data mode
D/C = 1
(1 SCLK cycle)
k
display data byte m
(8 SCLK cycles)
k+1
stop data transmission
SCE = 1
MGW717
Fig.44 Write sequence to RAM, advanced protocol.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
11.2.2 READ MODE (COMMAND REGISTER ONLY)
PCF8832
The PCF8832 samples the SDI data at rising SCLK edges, but shifts SDO data at falling SCLK edges. Thus the host microcontroller must read SDO data at rising SCLK edges. The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge. The last rising SCLK edge sets SDO to 3-state after the delay time tODE2.
The interface read mode means the microcontroller reads data from the PCF8832. To do this the microcontroller first sends a command sequence, then transmits the following byte in the opposite direction (using SDO). After that, SCE is required to go HIGH before a new command can be sent.
handbook, full pagewidth
1
start data transmission
SCE = 0
2
command mode
D/C = 0
(1 SCLK cycle)
3
control byte
1
0
ADR [5:0] = 01H
(8 SCLK cycles)
4
command mode
D/C = 0
(1 SCLK cycle)
5
register value = 02H
RSTA = 1
(8 SCLK cycles)
6
command mode
D/C = 0
(1 SCLK cycle)
7
control byte
1
0
ADR [5:0] = n
(8 SCLK cycles)
8
read register from ADR = n
(8 SCLK cycles)
9
stop data transmission
SCE = 1
RSTA = 0
MGW718
Fig.45 Read from register, basic protocol.
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
12 I2C-BUS INTERFACE 12.1 Characteristics of the I2C-bus (Hs-mode) 12.1.1 SYSTEM CONFIGURATION
PCF8832
Definitions of terms used: * Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
The I2C-bus Hs-mode is for bi-directional, two-line communication between different ICs or modules with speeds up to 3.4 MHz. The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate, therefore the buffers on the SCL and SDA outputs have an open drain. This is the same for I2C-bus master devices which have an open-drain SDA output and a combination of open-drain pull-down and current source pull-up circuits on the SCL output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.46 System configuration.
12.1.2
BIT TRANSFER
One data bit is transferred during each clock pulse (see Fig.47). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.47 Bit transfer.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
12.1.3 START AND STOP CONDITIONS
PCF8832
Both data and clock lines remain HIGH when the bus is not busy (see Fig.48). A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P).
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.48 Definition of start and stop conditions.
12.1.4
ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit (see Fig.49). The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.49 Acknowledge on the I2C-bus.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
12.2 I2C-bus Hs-mode protocol Table 21 Definition of CO CO 0 ACTION
PCF8832
The PCF8832 is a slave receiver/transmitter. If data is to be read from the device, the SDACK pin must be connected, otherwise SDACK may be unused. Hs-mode can only commence after the following conditions: * START condition (S) * 8-bit master code (00001XXX) * Not-acknowledge bit (A). The master code has two functions, it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner. Also the master code indicates the beginning of an Hs-mode transfer. In Figs 50 and 51 these conditions are visualized. As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A-bit, and the SCL line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCL signal (see Fig.51). The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a R/W-bit and receives an acknowledge bit (A) from the selected slave. After each acknowledge bit (A) or not-acknowledge bit (A), the active master disables its current-source pull-up circuit. The active master re-enables its current source again when all devices have released and the SCL signal reaches a HIGH level. The rising of the SCL is done by a resistor pull-up and so is slower, the last part of the SCL rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S-mode after a stop condition (P). A write sequence after the Hs-mode is selected (see Fig.53) is initiated with a START condition (S) from the I2C-bus master and this is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. After acknowledgement of a write (W) condition, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines CO and D/C, plus a data byte (see Table 21, Table 22 and Fig.52). The last control byte is tagged with a cleared most significant bit, the continuation bit CO. The control and data bytes are also acknowledged by all addressed slaves on the bus.
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow this control byte unless a STOP or RE-START condition is received
1
Table 22 Definition of D/C D/C 0 R/W 0 1 1 0 1 ACTION command byte will be decoded and used to set up the device command byte of requested ADR will be returned data byte will be stored in the display RAM RAM read-back is not supported
After the last control byte, depending on the D/C bit setting, a series of display data bytes or command data bytes may follow. If the D/C bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is updated automatically and the data is directed to the intended PCF8832. If the D/C bit of the last control byte was set to `0', these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8832. At the end of the transmission the I2C-bus master issues a STOP condition (P) and switches back to F/S-mode, however, to reduce the overhead of the master code, it is possible for a master to link a number of Hs-mode transfers, separated by repeated START conditions (Sr). A read sequence (Fig.53) follows after the Hs-mode is selected. The PCF8832 will immediately start to output the requested data until a NOT acknowledge is transmitted by the master. Before the read access, the user has to set the D/C bit to the appropriate value by a preceding write access. The write access should be terminated by a repeated START condition so that the Hs-mode is not disabled.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
F/S-mode
Hs-mode (current-source for SCLH enabled)
F/S-mode
S
MASTER CODE
A
Sr
SLAVE ADD. R/W
A
DATA (n bytes + ack.)
A/A P
Hs-mode continues
Sr SLAVE ADD.
MSC616
Fig.50 Data transfer format in Hs-mode.
handbook, full pagewidth
S SDA
8-bit Master code 00001xxx
A
t1 tH
SCL
1
2 to 5
6
7
8
9
F/S mode
Sr
7-bit SLA
R/W
A
n x (8-bit DATA
+
A/A)
Sr P
SDA
SCL
1
2 to 5
6
7
8
9
1 Hs-mode
2 to 5
6
7
8
9 If P then F/S mode If Sr (dotted lines) then Hs-mode
tH = MCS current source pull-up = Rp resistor pull-up
tFS
MCE005
Fig.51 Complete data transfer in Hs-mode.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
acknowledge from PCF8832
acknowledge from PCF8832
acknowledge from PCF8832
acknowledge from PCF8832
acknowledge from PCF8832
SS Sr 0 1 1 1 1 A A 0 A 1 D/C 10 slave address
control byte
A
data byte
A 0 D/C
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
R/W CO
2n 0 bytes
CO
1 byte
MGW719
Fig.52 Master transmits in Hs-mode to slave receiver; WRITE mode.
handbook, full pagewidth
slave address
control byte
slave address SS A Sr 0 1 1 1 1 A A 1 A 10
read byte
SS S01111AA0AC0 O 10
ADR [5:0]
register value
AP
R/W start condition
D/C repeated start condition
R/W stop condition acknowledge slave acknowledge master
MGW720
acknowledge slave
acknowledge slave
Fig.53 Master receives from slave transmitter; READ mode.
12.3
Command decoder
The command decoder identifies command words that arrive on the I2C-bus: * Pairs of bytes - first byte determines whether information is display or instruction data - second byte contains information * Stream of information bytes after CO = 0; display or instruction data depending on last D/C bit.
The most significant bit of a control byte is the continuation bit CO. If this bit is logic 1 it indicates that only one data byte, either command or RAM data, will follow. If the bit is logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM-data/command bit D/C. When this bit is logic 1, it indicates that a RAM-data byte will be transferred next. If the bit is logic 0, it indicates that a command byte will be transferred next.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VDD1 VDD2 VDD3 IDD ISS VI/VO II IO Ptot Tstg Tj Note logic supply voltage analog supply voltage analog supply voltage supply current negative supply current input/output voltage (any input/output) DC input current DC output current total power dissipation per package storage temperature junction temperature PARAMETER MIN. -0.5 -0.5 -0.5 -50 -50 -0.5 -10 -10 - -55 - MAX. +4.0 +4.0 +4.0 +50 +50 VDD + 0.5 +10 +10 300 +125 125
PCF8832
UNIT V V V mA mA V mA mA mW C C
1. Parameters are valid over the operating temperature range unless otherwise specified; all voltages are referenced to VSS1; unless otherwise specified.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
14 DC CHARACTERISTICS VDD1 = 1.5 to 3.3 V; VDD2 = VDD3 = 2.4 to 3.5 V; VSS1 = VSS2 = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD1 VDD2 VDD3 VCOL VCOL Rs(CA1), Rs(CA2) Logic VIL VIH IOL(SDA) ILI IDD(tot) IDD(pd) Ro(COL) Ro(Cq) Note 1. VDD1 = 1.8 V; VDD2 = VDD3 = 2.8 V; no display; display data = 0. LOW-level input voltage HIGH-level input voltage LOW-level output current input leakage current total supply current power-down mode supply current pads SDA; VOL = 0.4 V; VDD1 = 3.3 V VI = VDD1 or VSS1 note 1 note 1 VSS1 3.0 -1 - - - - - - - 260 25 0.2VDD1 V VDD1 - +1 1500 500 V mA A A A k 0.8VDD1 - logic supply voltage analog supply voltage analog supply voltage column driving voltage VCOL tolerance series resistance of pads CA1, CA2 for external capacitor Cq connection 1.5 2.4 2.4 2.5 -100 - - - - - 0 - 3.3 3.5 3.5 4.0 +100 10 V V V V mV PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Column outputs output resistance of column driver pads C0 to C383 series resistance for external DC-to-DC converter (CA1, CA2) 2 - 15 10
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
15 AC CHARACTERISTICS VDD1 = 2.5 to 3.3 V; VDD2 = VDD3 = 2.4 to 3.5 V; VSS1 = VSS2 = 0 V; Tamb = -40 to +85 C; note 1; unless otherwise specified. SYMBOL fframe fosc fclk(ext) tW(RESL) tSU;RESL PARAMETER LCD frame frequency oscillator frequency external clock frequency reset LOW pulse width reset LOW pulse set-up time after power-on see Fig.54 see Fig.54 CONDITIONS internal clock; VDD1 = 3.0 V note 2 20 - 400 500 0 MIN. TYP. 120 600 600 - - - - - - - - - - - - - - - - MAX. 400 - 800 - 1 UNIT Hz kHz kHz ns s
I2C-bus interface; Hs mode; see Fig.55 fSCL tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tfDA tSU;STO Cb tSW VnL VnH serial clock frequency set-up time (repeated) START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time fall time of SDA signal set-up time for STOP condition capacitive load for SDA and SCL lines tolerable spike width on bus noise margin at the LOW level for each connected device noise margin at the HIGH level for each connected device including hysteresis including hysteresis Hs-mode; note 3 F/S-mode 0 160 160 160 60 10 0 20 160 - - - 0.1VDD1 0.2VDD1 3.4 - - - - - 70 80 - 100 400 5 - - MHz ns ns ns ns ns ns ns ns pF pF ns V V
8-bit parallel (8080-type) interface; note 4; see Fig.56 tAH tAS TCYC tCCLW tCCLR tCCHW tCCHR tDS tDH tACC tOH D/C, CS address hold time D/C, CS address set-up time system cycle time WR control L pulse width RD control L pulse width WR control H pulse width RD control H pulse width D0 to D7 data set-up time D0 to D7 data hold time RD access time output disable time CL = 50 pF note 5 WRITE mode READ mode WRITE mode READ mode -5 10 160 20 40 15 15 20 10 - - - - - - - - - - - - - - - - - - - - 70 25 ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - - - - - - - - - - - - - - - - - - - - - -
MAX. - - - - - - - 30 70 - - - - - - - - - - - 50 100 - 50
UNIT
8-bit parallel (6800-type) interface; note 6; see Fig.57 TCYC tAS1 tAS2 tAH1 tAH2 tDS tDH tOH tACC tEH tEL TSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH tODE1 tODE2 tCEH tACC Notes 1. All timing values are valid within the operating ambient temperature and supply voltage ranges and are referred to VIL and VIH with an input voltage swing of VSS1 to VDD1. 2. Not directly observable at any pin. 3. Cb = total capacitance of one bus line in pF. 4. The input signal rise time and fall time (tr and tf) are specified at 15 ns or less. When the cycle time is used at high-speed, the specification is tr + tf (TCYC - tCCLW - tCCHW) or tr + tf (TCYC - tCCLR - tCCHR). 5. The system cycle time can be derated for different values of VDD1. For VDD1 < 2.5 V the system cycle time can be calculated as follows: at VDD1 = 2.5 V, fCYC(2.5) = 6.25 MHz and f = 0.44 MHz/V then f CYC(VDD1) = f CYC(2.5) x 0.44 x V DD1 MHz. 6. The input signal rise time and fall time (tr and tf) are specified at 15 ns or less. When the cycle time is used at high-speed, the specification is tr + tf (TCYC - tEH - tEL). 7. The input signal rise time and fall time (tr and tf) are specified at 15 ns or less. system cycle time D/C, CS address set-up time R/W address set-up time D/C, CS address hold time R/W address hold time D0 to D7 data set-up time D0 to D7 data hold time D0 to D7 output disable time D0 to D7 access time E pulse width HIGH E pulse width LOW CL = 50 pF 160 50 50 10 35 20 10 10 - 40 60 ns ns ns ns ns ns ns ns ns ns ns
Serial interface; note 7; see Figs 58, 59 and 60 serial clock SCLK period SCLK pulse width HIGH SCLK pulse width LOW D/C address hold time D/C address setup time SDI data set-up time SDI data hold time SCE to SCLK set-up time SCE to SCLK hold time SDO disable time SDO disable time SCLK to SCE hold time SCLK to SDO access time 160 60 60 70 45 45 50 30 120 - 25 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
VDD1
RES VIL t SU; RESL t W(RESL)
VDD1
RES VIL t W(RESL) t W(RESL)
MGW721
Fig.54 Reset timing.
handbook, full pagewidth
Sr tfDA
trDA
Sr
P
SDA
tSU;STA
tHD;DAT tHD;STA tSU;DAT
tSU;STO
SCL tfCL trCL1
(1)
trCL tHIGH tLOW tLOW tHIGH
trCL1
(1)
MCE006
= MCS current source pull-up = Rp resistor pull-up
(1) Rising edge of the first SCL clock pulse after an acknowledge bit.
Fig.55 I2C-bus timing diagram (Hs-mode).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
D/C t AS t AH
CS T CYC t CCLR, t CCLW WR, RD t DS D0 to D7 (write) t ACC D0 to D7 (read)
MGW722
t CHHR, t CHHW
t DH
t OH
Fig.56 8080 type - parallel interface timing.
handbook, full pagewidth
RW
D/C t AS1 t AH2 CS T CYC t AS2 E t DS D0 to D7 (write) t ACC D0 to D7 (read)
MGW723
t AH1
t EH
t EL
t DH
t OH
Fig.57 6800 type - parallel interface timing.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
t CSS
t CSH
SCE t SAS D/C T SCYC t SLW SCLK tf t SDS tr t SDH t SHW t SAH
SDI
MGW724
Fig.58 Serial interface timing.
handbook, full pagewidth
SCE t CEH SCLK t SDH t SDS
SDI
t ACC SDO
t ODE1
MGW725
Fig.59 Serial interface timing - read mode SPI 3 or 4-line.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
handbook, full pagewidth
SCE t CEH SCLK t SDH SDI t SDS
t ACC SDO
t ODE2
MGW726
Fig.60 Serial interface timing - read mode serial interface 3-line.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
16 APPLICATION INFORMATION
PCF8832
The pinning of the PCF8832 is organized for single plane wiring, for example chip-on-glass, TCP and COF display modules. The display size is 160 x 128 RGB STN pixels. The host microcontroller and the PCF8832 are both connected to the interface bus.
handbook, full pagewidth
to row driver
LCD PANEL
384 columns
VCOL VM I/O BUFFER INTERFACE 16 Cd2 Cd1 control inputs/outputs Cq
PCF8832
VDD1 VDD2 VDD3 VSS1 VSS2 CA1 CA2
VDD(logic) VDD(analog) VSS
MGW661
Fig.61 Application configuration (master/slave control inputs and row driver signal not shown).
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
VDD handbook, full pagewidth
VDD VH R0 R1 VMH 160 R2
PCF8831
VL T1 to T5 (1) R159
LCD DISPLAY (128 x 160 dots)
VCOL
VM VSS C0 9 (2) Row control VM VCOL LCK
384 C383
PCF8832
LCK
FBQ CA1 VDD1 VDD3 VDD2 VSS
MGW637
CA2
(1) Test inputs T1 to T5 have to be tied to VSS. (2) Row control signals are RCLK, RP, FI, SVM, ROWRES1, ROWRES2, SW1, SW2 and R1F.
Fig.62 Application example using PCF8831 with PCF8832.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
17 INTERNAL PROTECTION CIRCUITS
VDD1 VDD2
PCF8832
handbook, full pagewidth
VDD3
VSS1
VSS1 VSS2
VSS1
VCOL VSS2 VCOL C0 to C383
VSS1
VSS1
VSS1
VDD1
VDD2
D0, D1, D2, D3, D4, D5, D6, D7, FSYN
RESROW, RCLK, RP, FI
VSS1
VSS1
VDD3
VDD1
VDD2
FBQ
T3, T4
LCK, SVM, R1F, SW1, SW2
VSS1
VSS1
VSS1
VDD1 OSC, CS, D/C, RD, WR, RES, PS2, PS1, PS0, LPOS, CSCD, AOFF, TP1, TP2, TP3, TP4, TP5, ID0, ID1, ID2, T1, T2, T5, T6, T7, T8, T9, T10 VSS1
VDD1 SCL, SDA
VSS1
VDD1 CA1, CA2 SDACK
VSS1 Protection diode maximum forward current = 5 mA; maximum reverse voltage = 4 V.
VSS1
MGW729
Fig.63 Protection circuit diagrams.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
18 BONDING PAD INFORMATION
PCF8832
handbook, full pagewidth
PS2 PS1 PS0 AOFF CSCD LPOS ID2 ID1 ID0 T2 T5 OSC T1 TP4 TP3 TP2 TP1 TP0
T4 FBQ T6 T7 T8 LCK
RESROW SVM
VDD3
VDD2
VDD1
VSS1
VSS2
VCOL
dummy bumps
RCLK FSYN C383 C336 RP FI
CA2
CA1
SW2
SW1
T10 T9
VM
pad 164
PC8832-1
y
R1F
C335
0,0
x
C312
pad 357
C168
alignment circle 1 dummy bump pad 1 dummy bumps
C47 C0 SCL SDACK SDA T3 D/C WR RES
RD
CS
D7
D6
D5
D4
D3
D2
D1
D0
pad 165
C48
C71
pad 356
C167
C72
MGW728
alignment circle 2 dummy bumps
Fig.64 Location of bonding pads (refer also to Table 23).
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C311
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
Table 23 Bonding pad locations All x and y coordinates are referenced to the centre of the chip (dimensions in m; see Fig.64). COORDINATES SYMBOL dummy 6 C312 C313 C314 C315 C316 C317 C318 C319 C320 C321 C322 C323 C324 C325 C326 C327 C328 C329 C330 C331 C332 C333 C334 C335 dummy 7 dummy 8 dummy 9 C336 C337 C338 C339 C340 C341 C342 C343 C344 2002 Aug 16 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 6874 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6875 6874 6821 6768 6715 6662 6609 6556 6503 6450 6397 6344 6291 y -1000 -635.8 -582.8 -529.8 -476.8 -423.8 -370.8 -317.8 -264.8 -211.8 -158.8 -105.8 -52.8 0.2 53.2 106.2 159.2 212.2 265.2 318.2 371.2 424.2 477.2 530.2 583.2 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 63
PCF8832
COORDINATES SYMBOL C345 C346 C347 C348 C349 C350 C351 C352 C353 C354 C355 C356 C357 C358 C359 C360 C361 C362 C363 C364 C365 C366 C367 C368 C369 C370 C371 C372 C373 C374 C375 C376 C377 C378 C379 C380 C381 C382 C383 PAD x 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 6238 6185 6132 6079 6026 5973 5920 5867 5814 5761 5708 5655 5602 5549 5496 5390 5337 5284 5231 5178 5125 5072 5019 4966 4913 4860 4807 4754 4701 4648 4595 4542 4489 4436 4383 4330 4277 4224 4171 y 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
COORDINATES SYMBOL FSYN RCLK RP FI SVM RESROW R1F SW1 SW2 VM VM VM VM VM VM LCK T8 T7 T6 FBQ T4 VCOL VCOL VCOL VCOL VCOL VCOL CA1 CA1 CA1 CA1 CA1 CA1 CA2 CA2 CA2 CA2 CA2 CA2 PAD x 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 4012 3853 3694 3535 3376 3217 3058 2899 2740 2634 2581 2528 2475 2422 2369 2316 2263 2210 2157 2104 2051 1998 1945 1892 1839 1786 1733 1680 1627 1574 1521 1468 1415 1362 1309 1256 1203 1150 1097 y 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000 1000 1000 1000 1000 1000 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 TP0 TP1 TP2 TP3 TP4 T1 OSC T5 T2 ID0 ID1 ID2 LPOS CSCD AOFF PS0 PS1 PS2 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 SYMBOL PAD
COORDINATES x 1044 991 938 885 832 779 726 673 620 567 514 461 408 355 302 249 196 143 90 37 -16 -69 -122 -175 -228 -281 -334 -387 -440 -493 -546 -599 -652 -705 -758 -811 -864 -917 -970 y 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000 1000 1000 1000 1000 1000 1000 1000 1000
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
COORDINATES SYMBOL VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 T9 T9 T10 T10 D0 D1 D2 D3 D4 D5 D6 D7 RES CS RD WR DC T3 SDA SDA SDACK SCL SCL C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 PAD x 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 -1 023 -1076 -1129 -1182 -1235 -1288 -1394 -1447 -1553 -1606 -1712 -1871 -2030 -2189 -2348 -2507 -2666 -2825 -2984 -3143 -3302 -3461 -3620 -3673 -3779 -3832 -3938 -4044 -4097 -4203 -4256 -4309 -4362 -4415 -4468 -4521 -4574 -4627 -4680 y 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000.1 1000 1000.1 1000.1 1000.1 1000.1 1000.1 1000.1 1000 1000.1 1000.1 1000.1 1000.1 1000.1 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 dummy 1 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 SYMBOL PAD
COORDINATES x -4733 -4786 -4839 -4892 -4945 -4998 -5051 -5104 -5157 -5210 -5263 -5316 -5369 -5422 -5528 -5581 -5634 -5687 -5740 -5793 -5846 -5899 -5952 -6005 -6058 -6111 -6164 -6217 -6270 -6323 -6376 -6429 -6482 -6535 -6588 -6641 -6694 -6747 -6800 y 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
COORDINATES SYMBOL dummy 2 dummy 3 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 dummy 4 dummy 5 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 PAD x 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 -6853 -6906 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6875 -6906 -6694 -6588 -6535 -6482 -6429 -6376 -6323 -6270 -6217 -6164 -6111 -6058 y 1000 1000 540.2 487.2 434.2 381.2 328.2 275.2 222.2 169.2 116.2 63.2 10.2 -42.8 -95.8 -148.8 -201.8 -254.8 -307.8 -360.8 -413.8 -466.8 -519.8 -572.8 -625.8 -678.8 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 SYMBOL PAD
COORDINATES x -6005 -5952 -5899 -5846 -5793 -5740 -5687 -5634 -5581 -5528 -5475 -5422 -5369 -5263 -5210 -5157 -5104 -5051 -4998 -4945 -4892 -4839 -4786 -4733 -4680 -4627 -4574 -4521 -4468 -4415 -4362 -4309 -4256 -4203 -4150 -4097 -4044 -3938 -3885 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
COORDINATES SYMBOL C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 PAD x 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 -3832 -3779 -3726 -3673 -3620 -3567 -3514 -3461 -3408 -3355 -3302 -3249 -3196 -3143 -3090 -3037 -2984 -2931 -2878 -2825 -2772 -2719 -2613 -2560 -2507 -2454 -2401 -2348 -2295 -2242 -2189 -2136 -2083 -2030 -1977 -1924 -1871 -1818 -1765 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C190 C191 C192 C193 C194 C195 C196 C197 C198 C199 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 SYMBOL PAD
COORDINATES x -1712 -1659 -1606 -1553 -1500 -1447 -1394 -1288 -1235 -1182 -1129 -1076 -1023 -970 -917 -864 -811 -758 -705 -652 -599 -546 -493 -440 -387 -334 -281 -228 -175 -122 -69 143 196 249 302 355 408 461 514 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
COORDINATES SYMBOL C200 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 C233 C234 C235 C236 C237 C238 PAD x 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 567 620 673 726 779 832 885 938 991 1044 1097 1150 1203 1256 1309 1362 1468 1521 1574 1627 1680 1733 1786 1839 1892 1945 1998 2051 2104 2157 2210 2263 2316 2369 2422 2475 2528 2581 2634 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 C239 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249 C250 C251 C252 C253 C254 C255 C256 C257 C258 C259 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 C275 C276 C277 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 SYMBOL PAD
COORDINATES x 2687 2793 2846 2899 2952 3005 3058 3111 3164 3217 3270 3323 3376 3429 3482 3535 3588 3641 3694 3747 3800 3853 3906 3959 4012 4118 4171 4224 4277 4330 4383 4436 4489 4542 4595 4648 4701 4754 4807 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
Table 24 Bonding pad dimensions ITEM Minimum pad pitch Pad size; aluminium Bump dimensions Wafer thickness (excluding bumps) 53 43 x 105
PCF8832
COORDINATES SYMBOL C278 C279 C280 C281 C282 C283 C284 C285 C286 C287 C288 C289 C290 C291 C292 C293 C294 C295 C296 C297 C298 C299 C300 C301 C302 C303 C304 C305 C306 C307 C308 C309 C310 C311 PAD x 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 4860 4913 4966 5019 5072 5125 5178 5231 5284 5337 5443 5496 5549 5602 5655 5708 5761 5814 5867 5920 5973 6026 6079 6132 6185 6238 6291 6344 6397 6450 6503 6556 6609 6662 -6800 6777.5 y -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000 -1000
DIMENSIONS
UNIT m m m m
33 x 95 x 15 (5) 381
handbook, halfpage
14.08 mm
2.33 mm
PCF8832
pitch
y
x
MGW727
Fig.65 Bonding pad dimensions.
handbook, halfpage
y centre
100 m
x centre
MGS688
Alignment marks (see Fig.66) Alignment circle 1 Alignment circle 2 Fig.66 Alignment circle detail.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
19 TRAY INFORMATION
PCF8832
handbook, full pagewidth
x
A C
y
1,1 1,2 x,1
D
B F
1,y
x,y
E
MGW730
The dimensions are given in Table 25.
Fig.67 Tray details.
Table 25 Tray dimensions DIMENSION A
handbook, halfpage
DESCRIPTION pocket pitch x direction pocket pitch y direction pocket width x direction pocket width y direction tray width x direction tray width y direction number of pockets in x direction number of pockets in y direction
VALUE 20.32 mm 4.32 mm 14.18 mm 2.44 mm 50.8 mm 50.8 mm 2 10
B C D
PF8832-1
E F
MGW731
- -
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to Fig.64 for the orientation and position of the type name on the die surface.
Fig.68 Tray alignment.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
20 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
PCF8832
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 21 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products 2002 Aug 16 71 for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
23 PURCHASE OF PHILIPS I2C COMPONENTS
PCF8832
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
NOTES
PCF8832
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
NOTES
PCF8832
2002 Aug 16
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Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
NOTES
PCF8832
2002 Aug 16
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/01/pp76
Date of release: 2002
Aug 16
Document order number:
9397 750 09123

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